Architecture

By the standards of general-purpose processors, DSP instruction sets are often highly irregular. One implication for software architecture is that hand-optimized assembly-code routines are commonly packaged into libraries for re-use, instead of relying on advanced compiler technologies to handle essential algorithms.
Hardware features visible through DSP instruction sets commonly include:
Hardware modulo addressing, allowing circular buffers to be implemented without having to constantly test for wrapping.
A memory architecture designed for streaming data, using DMA extensively and expecting code to be written to know about cache hierarchies and the associated delays.
Driving multiple arithmetic units may require memory architectures to support several accesses per instruction cycle
Separate program and data memories (Harvard architecture), and sometimes concurrent access on multiple data busses
Special SIMD (single instruction, multiple data) operations
Some processors use VLIW techniques so each instruction drives multiple arithmetic units in parallel
Special arithmetic operations, such as fast multiply–accumulates (MACs). Many fundamental DSP algorithms, such as FIR filters or the Fast Fourier transform (FFT) depend heavily on multiply–accumulate performance.
Bit-reversed addressing, a special addressing mode useful for calculating FFTs
Special loop controls, such as architectural support for executing a few instruction words in a very tight loop without overhead for instruction fetches or exit testing
Deliberate exclusion of a memory management unit. DSPs frequently use multi-tasking operating systems, but have no support for virtual memory or memory protection. Operating systems that use virtual memory require more time for context switching among processes, which increases latency.
editProgram flow
Floating-point unit integrated directly into the datapath
Pipelined architecture
Highly parallel multiplier–accumulators (MAC units)
Hardware-controlled looping, to reduce or eliminate the overhead required for looping operations
editMemory architecture
DSPs often use special memory architectures that are able to fetch multiple data and/or instructions at the same time:
Super Harvard architecture
Harvard architecture
Modified von Neumann architecture
Use of direct memory access
Memory-address calculation unit
editData operations
Saturation arithmetic, in which operations that produce overflows will accumulate at the maximum (or minimum) values that the register can hold rather than wrapping around (maximum+1 doesn't overflow to minimum as in many general-purpose CPUs, instead it stays at maximum). Sometimes various sticky bits operation modes are available.
Fixed-point arithmetic is often used to speed up arithmetic processing
Single-cycle operations to increase the benefits of pipelining
editInstruction sets
Multiply–accumulate (MAC, including fused multiply–add, FMA) operations, which are used extensively in all kinds of matrix operations, such as convolution for filtering, dot product, or even polynomial evaluation (see Horner scheme)
Instructions to increase parallelism: SIMD, VLIW, superscalar architecture
Specialized instructions for modulo addressing in ring buffers and bit-reversed addressing mode for FFT cross-referencing
Digital signal processors sometimes use time-stationary encoding to simplify hardware and increase coding efficiency